1. Field of the Invention
This invention relates to a sample-and-hold circuit and more particularly to a sample-and-hold circuit arranged to sample and hold a given input signal and to output a sampled and held signal.
2. Description of the Related Art
In an image sensing device using a solid-state image sensor, information accumulated at each picture element of the solid-state image sensor (or a CCD image sensor) is arranged to be read out on a transfer clock signal as a video information signal. The signal read out from the CCD image sensor is arranged to be sampled and held in a cycle synchronized with the transfer clock signal for an ensuing signal processing operation.
However, an increase in number of the picture elements necessitates an increase in the speed of the transfer clock signal to be used for the image sensor. With the number of picture elements increased, the speed of sampling pulses to be used for sampling and holding the output of the image sensor also must be increased accordingly. As a result of the increase in the speeds of the transfer clock signal and the sampling pulses, a phase relation between output of the image sensor and the sampling pulses comes to be greatly affected even by a slight delay caused by the circuit arrangement.
FIG. 1(A) shows in outline the arrangement of the conventional sample-and-hold (hereinafter abbreviated as S/H) circuit. In FIG. 1(A), reference symbols a, b and c respectively denote an input terminal to which the output signal of the image sensor is inputted, an input terminal to which a clock signal is inputted and an output terminal. FIGS. 1(B), 1(C) and 1(D) respectively show the waveforms of the signal obtained at these terminals a, b and c at different points of phase.
As shown in FIG. 1(B), the image-sensor output signal inputted to the input terminal "a" shows a reset part, a reference part and a data part in a cycle. Among these parts, only the data part carries information as a video signal. In order that the video data is alone correctly taken out from the image-sensor output signal, the clock signal inputted to the terminal "b" must be precisely synchronized with the data part of the image-sensor output signal inputted to the terminal "a", as shown in FIG. 1(D).
If the phase relation between the input signal "a" and the clock signal "b" is deviating as shown in FIGS. 1(B) and 1(C), a pulse leak component would be generated in the output signal "c" obtained through a sample-and-hold process. The pulse leak component becomes an error signal in a subsequent signal processing action and thus comes to deteriorate picture quality. In addition to this problem, it has been another problem that the sample-and-hold output signal "c" obtained in this manner tends to bear incorrect image information, as shown in FIG. 1(B).